module top_module(
    input clk,
    input areset,    // Freshly brainwashed Lemmings walk left.
    input bump_left,
    input bump_right,
    input ground,
    input dig,
    output reg walk_left,
    output reg walk_right,
    output reg aaah,
    output reg digging  ); 
    
    reg[2:0] state,nstate;
    reg [7:0] cont;
    parameter left = 0,right=1,fl=2,fr=3,dl=4,dr=5,over=6;
    always @(*) begin
        if (ground==1) begin
            if (dig==1) begin
                case (state)
                   left:nstate=dl;
                   right:nstate=dr;
                    fl:nstate=(cont>=20)?over:left;
                    fr:nstate=(cont>=20)?over:right;
                    dl:nstate=dl;
                    dr:nstate=dr;
                endcase
            end else begin
                case (state)
                    left:nstate=bump_left?right:left;
                    right:nstate=bump_right?left:right; 
                    fl:nstate=(cont>=20)?over:left;
                    fr:nstate=(cont>=20)?over:right;
                    dl:nstate=dl;
                    dr:nstate=dr;
                endcase
            end


        end else begin
            case (state)
                left:nstate=fl;
                right:nstate=fr; 
                fl:nstate=fl;
                fr:nstate=fr;
                dl:nstate=fl;
                dr:nstate=fr;
            endcase
        end
        walk_left=(state==left);
        walk_right=(state==right);
        digging=((state==dr)||(state==dl));
        
    end

    always @(posedge clk or posedge areset) begin
        if (areset==1) begin
            state<=left;
            cont<=0;
        end else begin
            if ((state==fl)||(state==fr)) begin
                cont<=cont+1;
            end else begin
                cont<=0;
            end
            state<=nstate;
            if (ground==1) begin
                aaah<=0;
            end else begin
                if (state!=over) begin
                    aaah<=1;
                end
                
            end
        end

    end


endmodule
